This invention relates generally to a semiconductor device, and more particularly to a bipolar transistor having higher performance and capable of high density integration.
Higher performance and higher integration density have been required for semiconductor devices having bipolar transistors of the recent types (semiconductor bipolar integrated circuits). A structure shown in FIG. 1 of the accompanying drawings has been proposed in order to improve performance of a bipolar transistor (refer to Japanese Patent Laid-Open No. 1556/1981).
In FIG. 1, reference numeral 1 represents a P-type Si (silicon) substrate, 2 is a high concentration N-type collector buried layer, 12 is a channel stopper layer, 19 is a SiO.sub.2 (silicon dioxide) film for device isolation, 20 is a high concentration N-type impurity doped layer for taking out a collector electrode, 21 is a high concentration P-type base region, 24 is a high concentration N-type emitter region, 18 is a polycrystalline Si film for taking out a base electrode, 22 is a passivation film made of Si.sub.3 N.sub.4 (silicon nitride) or PSG (phosphosilicate glass), 25 a base electrode, 26 is an emitter electrode and 27 is a collector electrode.
The conventional semiconductor device having the structure shown in FIG. 1 is characterized in that the emitter 24, base 21 and collector 2' below the base 21 of the bipolar transistor are formed inside a protruding portion of the silicon substrate, and the base extension electrode consisting of the polycrystalline silicon film 18 into which large quantities of impurity is doped and which has low resistance is connected to the side portion of the base 21. Hereinafter, this structure will be referred to as "SICOS (Sidewall Base Contact Structure)".
Such an SICOS semiconductor device is extremely effective for reducing the size of the bipolar transistor itself and for improving the performance of the transistor, but since the area of isolation regions between the devices is great, the semiconductor device is not suitable for high density integration.
A structure shown in FIG. 2 has been proposed in order to solve the problem described above (refer to Japanese Patent Laid-Open No. 235460/1985).
In FIG. 2, like reference numerals are used to identify like constituents as in FIG. 1 (and this will also hold true of all the later-appearing drawings).
In FIG. 2, reference numeral 30 represents a shallow trench for isolating the emitter and the collector, 31 is a deep trench for device isolation which has a substantially U-shaped cross-section, and 14 is poly-Si packed into the deep trench 31.
The conventional semiconductor device shown in FIG. 2 is characterized in that the deep trench 31 for device isolation, which has a substantially U-shaped section, is formed in the proximity of the base region 21 and the collector region 20, with the rest of the structure being the same as that of the semiconductor device shown in FIG. 1. In other words, the semiconductor device shown in FIG. 2 isolates the devices by the deep trench to drastically reduce the area of the device isolation region and accomplishes the high integration density of the high performance bipolar integrated circuit.
In the conventional semiconductor device shown in FIG. 2, however, it is difficult to form the contact width between the poly-Si film 18 for taking out the base electrode and the base region 21 in the same size on the side of the deep trench 31 for device isolation as on the side of the shallow trench 30. In other words, this structure involves the problem that the contact width a on the side of the deep trench 31 is different from the contact width b on the side of the shallow trench 30, that is, on the right side and on the left side in FIG. 2. Namely, the contact width a on the side of the deep trench 31 becomes small while the contact width b on the side of the shallow trench 30 becomes great.
If the contact width exhibits variation (or if the shape of the impurity doped layer of the base region 21) changes, the characteristics of the transistor such as a breakdown voltage, parasitic capacitance, a current amplification ratio, a rise voltage (V.sub.BE), and the like, vary so that the operation of the integrated circuit gets unstable. If the contact width a on the side of the deep trench 31 becomes small, the base resistance becomes high and the operation speed of the transistor drops.